This invention relates to the manufacture of probe card assemblies used to test the electrical continuity of integrated circuits formed on semiconductor wafers, such as silicon or gallium arsenide.
In the standard design of probe cards for performing such testing, a multi-layered ceramic (MLC) plate is inserted between a probe head that has a plurality of small diameter probes positioned to contact circuitry on an integrated circuit under test and a printed circuit board (PCB) that interfaces with an electric meter or other piece of test equipment. The plate is a space transformer having electrically conductive lines with conductive vias extending therethrough. The purpose of the MLC space transformer is to re-route electrical signals from the very finely pitched pattern of electrical contacts on the probe head to the more coarsely pitched pattern on the printed circuit board. By xe2x80x9cpitchedxe2x80x9d it is meant that there exists spacing between adjacent lines or vias. In the process of testing an integrated circuit, electrical connection must be made between the MLC and the printed circuit board. Such a connection is typically achieved by soldering the MLC to the PCB using industry standard soldering techniques to form a rigid solder connection. When conducting such testing at elevated temperatures, for example between 75 degrees and 125 degrees Celsius, it is desirable to manufacture the probe head out of materials whose Coefficient of Thermal Expansion (CTE) closely matches that of silicon wafer being tested. The CTE of silicon is 3.2 ppm/degC. Accordingly, it is preferred that the CTE of the probe head be approximately 2 times that of silicon, such as less than 7 ppm/degC.
Because the MLC makes electrical contact with the finely pitched contacts on the probe head, it too must have a CTE closely matching that of silicon. Preferably, the CTE of the MLC is also within 2 times of the CTE of silicon. This requirement presents a problem when mating the MLC to the PCB, as the CTE of PCB is typically 17 ppm, much higher than that of silicon. Because of the differing rates of expansion between the MLC and the PCB, there is a potential for the rigid solder connections to crack under the mechanical stress that results from heating and/or cooling the structure.
Typically, all probes of the probe head must be planar within a tolerance of a few thousandths of an inch. Careful control of manufacturing and assembly tolerances, as well as additional grinding and polishing processes, are required to maintain such a degree of planarity.
Existing circuitry testing methods and apparatuses do not account for this difference of CTEs. For example U.S. Pat. No. 5,623,213 entitled xe2x80x9cMembrane Probing of Circuitsxe2x80x9d and U.S. Pat. No. 5,841,291 entitled xe2x80x9cExchangeable Membrane Probe Testing of Circuitsxe2x80x9d are directed to the use of electrically conductive bumps on a flexible substrate or membrane to test electrical circuits. There is no suggestion or discussion that the system compensates for the differences of CTE inherent in the overall system.
Likewise, U.S. Pat. No. 5,973,504 entitled xe2x80x9cProgrammable High-Density Electronic Device Testingxe2x80x9d is directed to a system for testing high-density electronic devices. More particularly, this patent discloses the use of a test system with a multi-chip module to route signals between pads of a device under test and a test circuit. This system employs a membrane probe card and conductive circuit connection bumps. The membrane probe card is screwed onto the housing using a frame ring and is positioned between a pressure mechanism and the device under test. The conductive bumps are grouped on the membrane to correspond with the connection pad arrays. In an alternative embodiment, electrical connection may be maintained using electrical button connectors. Again there is no suggestion that the system be designed to compensate for the differences of CTE inherent in the testing system.
U.S. Pat. No. 5,623,213 entitled xe2x80x9cMembrane Probing of Circuits,xe2x80x9d U.S. Pat. No. 5,841,291 entitled xe2x80x9cExchangeable Membrane Probe Testing of Circuits,xe2x80x9d and U.S. Pat. No. 5,973,504 entitled xe2x80x9cProgrammable High-Density Electronic Device Testingxe2x80x9d are incorporated by reference herein in their entireties.
Commonly owned U.S. Pat. Nos. 6,163,162 and 6,297,657, both entitled xe2x80x9cTemperature Compensated Vertical Pin Probing Device,xe2x80x9d are directed to improved probing devices useful in testing integrated circuits over large temperature ranges. Both of these patents disclose methods and apparatuses complementary to the method and apparatus disclosed herein. U.S. Pat. Nos. 6,163,162 and 6,297,657 are incorporated by reference herein in their entireties.
Accordingly, there is a need for a method and apparatus useful to adjust the planarity of the probe head after assembly in order to correct for misalignment. Ideally, such a method and apparatus should minimize the need for critical machining and assembly processes.
It is an object of the invention to find a method of electrically and mechanically connecting the MLC to the PCB in a way that will allow for the differing rates of expansion while maintaining electrical contact.
Additionally, it is an object of the invention to provide a process whereby one may adjust the planarization of the MLC relative to the PCB.
One novel aspect of the present invention involves the attachment of the MLC to the PCB in a manner that allows for differing rates of thermal expansion as well as allowing for probe head planarization, while maintaining electrical contact between the MLC and the PCB.
To compensate for the differing rates of thermal expansion, the present invention suitably employs a planarizing interposer that includes a plate positioned between the MLC and the PCB while maintaining a compliant electrical connection. For the purposes of this disclosure, xe2x80x9ccompliant electrical connectionxe2x80x9d shall refer to a connection that maintains electrical connection and the integrity of the components on either side of the interconnection regardless of differing rates of thermal expansion, and allows for planarization of the head assembly. Compliant electrical connection with the device under test (integrated circuit) may be maintained using fuzz buttons or conductive bumps. In embodiments where fuzz buttons are used, the plate has a plurality of holes (also called vias or via holes) drilled in a pattern that matches the pattern of electrical contacts on the PCB. Fuzz buttons are then positioned within the holes. In embodiments where conductive bumps are employed, the conductive bumps are screened or deposited onto land grid array pads of the MLC and/or the PCB.
In a first embodiment, there is disclosed a probe card assembly for testing integrated circuits comprising: a multi-layered dielectric plate interposed between a probe head and a printed circuit board, the printed circuit board having arrayed upon its surface a first plurality of electrical contacts arranged in a pattern, the dielectric plate having arrayed upon its surface a second plurality of electrical contacts arranged in a pattern substantially matching the first plurality of electrical contacts; a planarizing interposer interposed between the ceramic plate and the printed circuit board, the planarizing interposer having a pattern of holes matching the pattern of electrical contacts on the printed circuit board and the dielectric plate; a mounting ring clamped to the plate and the mounting ring attached to the printed circuit board; and a third plurality of compliant electrical connectors disposed within a multiplicity of the holes arrayed in a pattern upon the planarizing interposer, the electrical connectors making electrical contact with the first plurality of electrical contacts and the second plurality of electrical contacts.
In a second embodiment, there is disclosed a method of adjusting the planarization of a probe card assembly comprising the steps of: (a) screwing the adjustment screws sufficiently tightly so as render the mounting ring in close proximity with the printed circuit board; (b) determining the planarization of said probe head; and (c) adjusting the tightness of the screws to achieve a desired degree of planarization for the probe head.
In a third embodiment, there is disclosed a method of assembling a probe card assembly comprising the steps of: (a) inserting each of a plurality of fuzz buttons into via holes using an electrically conductive tool; and (b) confirming electrical connectivity between the multi-layered dielectric plate and the printed circuit board.
In a fourth embodiment, there is disclosed a method of assembling the probe card assembly of claim 1, comprising the steps of: (a) providing a temporary plate to verify electrical connection; and (b) replacing the temporary plate with a multi-layered dielectric prior to testing.